SMTA International Conference Proceedings


Authors: Heather McCormick, Lee Smith, Jimmy Chow, Ahmer Syed, Corey Reichman and CJ Berry
Company: Celestica Inc. and Amkor Technology Inc.
Date Published: 10/4/2009   Conference: SMTA International

Abstract: Since their introduction, package on package components have proven popular, particularly in handheld portable applications. These packages offer significant advantages, including increased density through stacking of logic and memory devices in the same component footprint, and flexibility as a result of the assembler’s ability to select different memory devices for inclusion in the stack. Next generation versions of Package on Package devices are now emerging which offer improvements in component warpage during reflow and increased pin count due to pitch reduction on both the top and bottom package. This study focused on different assembly variations for a new 14 mm square package on package component with a 0.4mm pitch array on the lower package and 0.5mm pitch array on the upper package. This configuration allows for 620 I/O on the lower package, and 200 I/O on the upper package. The lower package in the stack featured a through mold via (TMV) structure, which reduces component warpage, and improves assembly yield. Flux Dip and Paste Dip were assessed for assembly of the upper package in terms of assembly yield, mechanical shock and thermal cycling reliability. Two different underfill materials were assessed for use on these components – one selected for optimal shock test performance, and one selected to optimize thermal cycling reliability. All assembly variations were subjected to accelerated thermal cycling (ATC) from -40°C to 125°C with a planned test duration of 2000 cycles. Mechanical shock testing was performed on a sub-set of the assembly variations to complete the reliability assessment.

Key words: 3-D packaging, package-on-package (PoP), stacked package, high density interconnect

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