ICSR (Soldering and Reliability) Conference Proceedings


ELECTROPLATE BUMPING WITHOUT PHOTORESIST AND SI DICE STACKING WITH TSV FOR 3D PACKAGING

Authors: Jiheon Jun, Inrak Kim, Younggon Lee and Jae Pil Jung
Company: Materials Science & Engineering, University of Seoul; Amkor Korea; and Mechanical Engineering, University of Waterloo
Date Published: 5/22/2009   Conference: ICSR (Soldering and Reliability)


Abstract: A novel process of direct solder bumping on a Si wafer without PR (Photoresist), namely non-PR bumping, and stacking of TSV (Through Silicon Via) embedded Si dice were investigated to achieve cost reduction and higher productivity in three dimensional electronics packaging. The stacking of bumped Si dice, produced by non-PR method, was studied as well. Vias were produced by the DRIE (Deep Reactive Ion Etching) on the Si wafer with 40µm in diameter. SiO2, Ti and Au layers were formed on the via wall and pulsed wave electroplating was applied to plug the via with Cu. Then the Si wafer was grinded by CMP (Chemical Mechanical Polishing) to the thickness of 70µm until the both sides of Cu plugged vias were exposed. DC (Direct Current) electroplating was performed to fabricate Sn and near eutectic Sn-Ag bumps on the Cu plugged vias in the Si die. The reduction current was supplied through the Cu plugging to its top surface for solder bumping. To optimize the plating process, the current density and plating time were varied up to 40mA/cm2 and 60 min, respectively. Bumped Si dice were stacked and assembled by reflow soldering in air at 255°C. The solder bumps were fabricated successfully without PR on the Cu plugged vias. The periphery of the bump was not so round as that with PR. However, it had an almost round periphery, and the surface of the bump showed a facet growth in Sn bumps while Sn-Ag bumps presented composite morphologies of hemispheric shape with Ag dendrites on their surface. The weight percent of Ag in Sn-Ag bumps were close to eutectic Sn-Ag composition. Three layers of Si dice with Sn bumps were stacked and assembled without any failure. In the bonding interface between Cu plug and solder bump, Cu6Sn5 IMC was observed by FESEM (Field Emission Scanning Electron Microscope) and EDS (Energy Dispersive Spectroscope) analysis. From these results, three dimensional stacking of TSV embedded Si dice and non-PR electroplating of micro bumps on vias were achieved successfully.

Key Words: wafer stacking, non-PR bumping, 3D packaging, through silicon via, solder bump



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