Pan Pacific Symposium Conference Proceedings


Authors: M. Juergen Wolf, Peter Ramm, and Herbert Reichl
Company: Fraunhofer Institute for Reliability and Microintegration IZM
Date Published: 2/12/2009   Conference: Pan Pacific Symposium

Abstract: Heterogeneous system integration is one of the key topics for future system integration. Scaling of System on Chip (SoC) alone does not address today’s requirements of smart electronic systems in terms of performance, functionality, miniaturization, low production cost and time to market. The traditional microelectronic packaging will more and more convert into complex system integration. “More than Moore” will be required due to tighter integration of system level components at the package level. This trend leads to advanced System in Package solutions (SiP) which require the synergy and a combination of wafer level and board integration technologies and which are rapidly evolving from a specialty technology used in a narrow set of applications to a high volume technology with wide ranging impact on electronics markets especially due to the high volume and very cost competitive consumer and communication market. Advanced SiP approaches explore the third dimension which results in complex system architectures that also require, beside new technologies and improved materials, adequate system design tools and reliability models. One of the most promising technology approaches is 3D packaging which involves a set of different integration approaches including stacked packages, silicon interposer with Through Silicon Vias (TSV) and embedding technologies. The paper highlights future system and potential technical solutions.

Key words: 3D integration, TSV, Wafer Level Packaging

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