Pan Pacific Symposium Conference Proceedings


Authors: Venky Sundaram, et al.
Company: Microsystems Packaging Research Center at Georgia Tech, Atotech, and Rogers Corporation
Date Published: 2/12/2009   Conference: Pan Pacific Symposium

Seika Machinery, Inc.

Abstract: In the past decade, mobile devices have supplanted computing applications as the primary drivers for package interconnection and wiring density. This shift to low-cost consumer products has resulted in the need for miniaturized, extremely low-profile and low-cost package substrates. The current leading-edge organic package substrates for portable device SiP and multi-component packages are based on 1+2+1 build-up construction on thin cores. The latest mobile product packaging roadmaps forecast a reduction in I/O peripheral pitch from 50-60µm to 20-30µm and I/O count per die increasing to more than 1000 within the next two to three years. Increasing adoption of embedded active and passive component solutions is adding to the wiring demand in the substrate. However, the increasing cost of high-density organic package substrates is a major concern for semiconductor, module and system companies.

The System-On-Package (SOP) concept, pioneered by Georgia Tech PRC, is focused on convergence of functions (digital, RF, optoelectronics, MEMS, etc) in a single package or module. Some of these fundamental packaging concepts have been implemented recently in an on-going, multi-year R&D program focused on embedded thin-film passive and active components (EMAP) for mobile product applications. This project is being jointly supported by semiconductor, systems and supply chain companies. A key technology building block in the EMAP research involves ultra-thin and low-loss organic substrates with an emphasis on minimizing cost. The research targets for this substrate are 50-100µm thick glass-reinforced laminate cores, 15-20µm thick build-up dry-film dielectric, 30-50µm diameter through-vias in the core, 25-40µm diameter blind microvias, and 15µm lines/spaces on both the core and build-up layers. The substrate is designed to match 30µm on-chip I/O pad pitch in a peripheral configuration with two chip sizes of 3mm x 3mm and 7mm x 7mm.

This paper describes results from collaborative research to achieve the wiring density of the 1+2+1 substrate within a two metal layer (2ML) thin core with filled through vias and ultra-fine lines. The reduction in layer count and elimination of build-up layer processing is anticipated to significantly reduce the substrate cost, thus enabling the organic substrate to be competitive with re-distribution layers used in wafer-level packaging. This research includes use of a state-of-the-art electroless and electrolytic copper plating process to achieve the required ultra fine line circuitry and through-via filling. These processes have been optimized on next-generation dielectrics characterized by ultra-low loss, low dielectric constant, low CTE and low moisture uptake with stable properties up to 40GHz. Results from various processes needed to achieve the super high-density 2ML substrate will be presented, as well as reliability evaluations of the completed substrate structures.

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