Pan Pacific Symposium Conference Proceedings


Authors: John Savic, et al.
Company: Cisco Systems, Inc.
Date Published: 2/12/2009   Conference: Pan Pacific Symposium

Abstract: High end computing and networking applications continue to drive silicon technologies for higher performance with increased bandwidth and frequency. This drive for higher performance has resulted in increased power dissipation. Mitigating the power dissipation can be achieved by reducing the voltage but unfortunately leads to reduced noise margin. In this study we measure power noise and make conclusions to the relative overall performance of various new packaging solutions.

This paper evaluates the electrical performance and assesses the design tradeoffs of two new packaging concepts and compares the data to a conventional high volume manufacturing ASIC (Application Specific Integrated Circuit) packaging solution. The baseline ASIC was redesigned into two advanced package configurations: (1) a package utilizing a conventional 4-4-4 substrate with SMT components interspersed between the BGA (ball grid array) balls, and (2) a package utilizing a 9+1 coreless substrate. A volume production 40 mm x 40 mm package with a 14 x 14 mm functional ASIC die assembled onto a standard build up 4-4-4 substrate running different traffic patterns in an actual switch/router blade server was used as the baseline for comparison.

Substrate level, package level and system level electrical performance tests were performed. Models for power plane impedance and core power noise were extracted using PowerSI [1] and simulated using HSPICE [2] for each new technology and compared to the baseline ASIC. Special test points were designed onto the substrates and custom lids were used to facilitate measurements under different traffic patterns and payloads. All results were compared with the production baseline ASIC design.

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