Pan Pacific Symposium Conference Proceedings


Authors: Makoto Motoyoshi, Hirofumi Nakamura, and Manabu Bonkohara
Company: ZyCube Co., Ltd.
Date Published: 2/12/2009   Conference: Pan Pacific Symposium

Abstract: Recently the development of three-dimensional large-scale integration (3D-LSI) has been accelerated and its stage has changed from the research level or limited production level to the investigation level with a view to mass production. There are many potential applications for 3D-LSI. Among them, the Chip size package (CSP) for CMOS image sensor has simplest structure which is fabricated by using 3D-LSI technology, so it is suitable as the vehicle for the development.

In this paper, the process and structure of the CSP for CMOS image sensors using current and advanced 3D-LSI technology are presented. Using the current technologies, CSPs for 1.3M, 2M, and 5M pixel CMOS image sensors are successfully fabricated without performances degradation. One of many potential applications for 3D-LSI is the high performance focal plane array image sensors. We propose the high-speed image sensor with 100% optical fill factor by using next generation 3D-LSI technology with µ-bump and µ-through silicon via (TSV).

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