DOE FOR PROCESS VALIDATION INVOLVING NUMEROUS ASSEMBLY MATERIALS AND TEST METHODSAuthors: Renee Michalkiewicz, Gaylon Morris, and Simin Bagheri
Company: Trace Laboratories, Inc. and Celestica, Inc.
Date Published: 2/12/2009 Conference: Pan Pacific Symposium
J-STD-001D, Appendix C focuses on process validation via Surface Insulation Resistance (SIR) Testing. The limitation to relying solely on SIR testing is its inherent inability to detect possible assembly issues which could result from employed combinations of printed circuit boards, solder masks, soldering materials (flux, paste, cored wire, rework flux, paste flux, etc.), adhesives, and inks. The authors' intention with this paper is to describe two Designs of Experiments (DOE’s) that were developed for process validation. The first relies on SIR testing as the sole means of qualifying the final assembly. The second explores the use of a broad range of tests chosen to closely represent the end use application.
DOE #1 was based upon the SIR testing procedure as per ANSI/J-STD-004, IPC-TM-650 22.214.171.124A the method which is also specified in J-STD-001. The scope of the test method is to determine the degradation of electrical insulation resistance of PCB specimens after exposure to specified materials. Since during the normal manufacturing process, a board assembly is exposed to a number of chemicals, for this DOE the standard SIR test coupons were prepared in such a way as to mimic a "typical" chemical mix that a board assembly may come in contact with during assembly. This involved applying the appropriate chemicals in the typical process order using appropriate process conditions.
Key words: Assembly Process Validation, Compatibility Matrix, Compatibility Testing, Compatibility Design of Experiment (DOE)
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