Pan Pacific Symposium Conference Proceedings


Author: Mark T. McMeen
Company: STI Electronics, Inc.
Date Published: 2/12/2009   Conference: Pan Pacific Symposium

Abstract: Do you know what level of applied strain your printed circuit board assembly realizes in your fielded state? This article looks at one case study of failed hardware and the underlying failure mechanisms of temperature cycling. Strain gage testing has been around for years. It has been used on specific applications to understand the applied strain and strain rates applied to printed circuit board assemblies from environmental forces during its working life. Today a renewed interest is stirring among component manufacturers, OEMs as well as contract electronic manufacturers due to the increased use of BGAs, micro BGA’s, and chip scale packages, as well as small form factor packaged components. The use of more lead-free alloys opens these finished assemblies up to fracturing due to CTE (coefficient of thermal expansion) fatigue and strain forces. Lead-free solder alloys are less ductile than 63/37 leaded solder alloys. These types of packaging formats with their reduced rigid solder interconnects are now susceptible to applied strain at these interfaces to the printed circuit card pads as well as to the component interface. Micro fracturing of the solder interconnect to the pad is the catastrophic failure. These defects are now common due to the density and shrink factor of these types of packages and the reduction in interconnect material volume.

Strain gage testing is the method of choice for quantitative analysis for evaluating the amount of strain that is being applied to these interconnects and package types due to their location on a particular design. This type of test evaluation allows process and design engineers to have the ability to assess strain across the board and its effect on a particular component in a certain location. This is valuable information needed for designing a circuit card assembly that needs to survive in an operating environment for 5 to 10 years. Strain pathways across the circuit card can be so localized that even standard chip style components can be fractured at their solder interface. To this end, strain gage testing allows the design engineer and process engineer the ability to assess component location as well as process related stress and strain due to manufacturing processes as well as environmental forces such as CTE movement and strain pathways over temperature cycling.

Component suppliers and final end use customers are starting to set limits on the amount of strain and strain rate levels seen on their components and final assemblies. This action is placing emphasis back onto the designer and process engineer to understand their processes and part location to insure that products meet their warranty and useful life periods. With this renewed interest and emphasis comes the need for the industry to determine limits and test protocols that are standardized to insure repeatability and consistency from manufacturer to end user. IPC / JDEC 9704 STANDARD is the industry standard that was released in 2005 to address standardization of strain gage testing. The challenge is in finding and setting the strain limits so that your design and component set are not jeopardized by elevated microstrain levels. Life cycle testing shows the amount of strain being applied during temperature cycling and the forces behind CTE fatigue fractures and strain pathway forces. The issue is long term reliability of finished assemblies in their operating environment and their ability to withstand the environmental forces.

STI’s Analytical Lab has taken a lead role in strain gage testing and data evaluation of applied strain and strain rate on printed circuit card assemblies. STI has also spent considerable time evaluating the effects of strain pathways due to the natural stiffening of certain areas of the card due to connector placement, large component packages, heat sink attachment devices, and other encapsulating material sets. These types of components have a large stiffening effect on a circuit card, location wise, and thus strain pathways are created around these components, which then creates high strain levels on certain other components in that strain pathway or corridor. CTE movement of these material sets used on the assembly play a large role in the applied stress being localized at certain locations on the board. Strain due to environmental forces combined with natural CTE movement can cause premature failure during the operating thermal cycles of an assembly. The review looks at the effect of CTE movement and strain in-parted from burn in and/or accelerated life cycling to determine the weak link in the overall design of the system. The use of the mathematical formula Y-X or X-Y to determine the peak-topeak amplitude and its corresponding delta difference from tension-to-compression or vice-versa is the essential information needed to determine impact over time. The ability to capture these data sets is essential to understanding where the greatest strain is located and its corresponding pathway. Also essential is the dwell or duration of stress over time which can be the silent killer in some applications because it is time dependent. This model is best used with a 170 temperature / time profile analysis overlaid with the strain gage data to capture time and temperature effects of CTE movement and strain levels on certain component locations. All testing was performed by the STI Electronics Analytical Lab on customer failed hardware.

Key words: Strain Gage, Microstrain Levels, Strain Rates, Strain Pathways, and Micro Fracturing

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