Pan Pacific Symposium Conference Proceedings


Authors: Laurence A. Harvilchuck, et al.
Company: Unovis Solutions, Intel Corporation, and Department of Systems Science and Industrial Engineering at SUNY Binghamton
Date Published: 2/12/2009   Conference: Pan Pacific Symposium

Abstract: There is scant data available to the process engineer to support the choice of PCB pad site dress methods from the perspective of potential printed circuit board damage. The thermal profile experienced by the pad array can have a profound impact on latent PCB damage, including the presence or absence of pad cratering. In this exercise, pad array damage is evaluated as a function of assembly preheating, pad site dress method, and applied desoldering temperature to offer insight when choosing between simple wick-and-iron solder removal and the more sophisticated vacuum–assisted solder scavenging methods.

High-resolution sixteen channel thermal profiles were obtained of both the wick-and-iron and vacuum scavenging operations across a single 34mm square pad array of variable pitch on a 0.060” thick lead-free ATX motherboard, revealing the nature of the thermal profile at the pad surface and through the board section to the cores. The shortcomings of current repair thermometry methods are also documented in the context of the impact of thermocouple placement on profile accuracy. Process variations that are inherent in the primarily manual wickand-iron solder removal methods are readily apparent in the thermal profiles experienced by the pad array, while significantly reduced in the thermal profile generated by the vacuum scavenger.

Wick-and-iron scavenging operations can subject the pad array to ramp rates approaching 200°C/second during the brief excursion above the solder liquidus, while vacuum scavenging of the same site exhibited a maximum ramp rate nearly a full order of magnitude less but of much greater times above liquidus. The impact of the thermal profile on the pad array was characterized by bump pull, pad fatigue and dye-and-pry techniques.

The results from the present study showed no solder mask damage in the vicinity of the pad array resulted from any of the scavenging processes. Damage to inner layer circuit board structures (per the IPC-610 standard) beneath the pad array was also absent in all cases under study. Use of substrate preheating during solder scavenging has a definite impact on reducing the substrate damage that can result from the repair of lead-free laminates. For both the wick-and-iron and vacuum methods, higher applied desoldering temperatures resulted in weaker pad adhesion than the corresponding solder removal operations at lower applied desoldering temperatures. Further pad fatigue testing of the same samples indicated that this change in pad adhesion strength may be related to a change in the ductility of the laminate directly beneath the pad. While the results presented here are based on a single laminate system, the choice of laminate supplier can also have a significant impact on the propensity for substrate damage during pad site dress.

Key words: repair, pad site dress, scavenging, board damage, pad cratering

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