Pan Pacific Symposium Conference Proceedings


Authors: Rozalia Beica and Paul Siblerud
Company: Semitool, Inc.
Date Published: 2/12/2009   Conference: Pan Pacific Symposium

Abstract: Increasing demands for electronic devices with greater functionality, superior performance in more compact and smaller packages has driven the semiconductor industry to develop more advanced packaging technologies. To address the limitations of two-dimensional configuration (2D), which has been the traditional approach to IC integration, in the past few years, new emerging technologies have been developed. Vertical integration proved to be essential in achieving a greater integration flexibility of different technologies, disparate devices, reason for which a general trend of transition from 2D to three-dimensional (3D) integration is currently being observed in the industry [1-5].

Among all the different types of 3D packaging technologies, 3D chip integration using through silicon via (TSV) copper is considered one of the most advanced technologies, and certainly, one of the hottest topics in the industry today.

There are different materials and methods that have been proposed and tested for TSV applications. Applicability of each material and method is limited by feature dimensions, final deposit characteristics and process reliability, practicability and last, but not least, cost considerations. Copper electrochemical deposition processes have several characteristics that make them attractive for various semiconductor applications, including TSV structure formation.

This paper will address various copper electrodeposition processes applied to form 3D interconnects. Advantages and difficulties associated with each of these technologies and the approaches taken to overcome them will be presented.

Reliable WLP structures of thick metal and high aspect ratios seem to be difficult to achieve when dry methods, such as physical vapor deposition (PVD) or chemical vapor deposition (CVD) are applied. New approaches, such as seed layer repair (SLE) or direct on barrier electrodeposition (DOB), can provide superior uniformity and coverage of the conductive layer, necessary for a uniform nucleation of copper electrodeposition for deep via filling, at significantly lower costs. TSV structures obtained with such techniques will be reviewed, along with the optimization work performed for achieving super conformal deep-via filling. Applying the optimum process parameters, void free TSV structures over a wide range of feature sizes and aspect ratios can be achieved. The effect of various factors that could considerably affect the performance, manufacturability and cost will be explained.

Integrated costs estimations associated with TSV for a viafirst approach, including a breakdown of the process steps will be presented.

Key words: TSV, through-silicon-via, 3D integrations, copper electrodeposition

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