INFRASTRUCTURE BUILDING FOR EMBEDDED DIE PRINTED WIRING BOARD APPLICATIONSAuthors: Theodore G. Tessier, et al.
Company: FlipChip International, LLC
Date Published: 10/13/2008 Conference: IWLPC (Wafer-Level Packaging)
Beginning in 2009, high volume deployment of these technologies is expected to begin. A key part of this developing supply chain relates to modification and standardization of integrated circuits, integrated passives and other device technologies for embedding. Wafer level redistribution has been demonstrated to be a very cost-effective approach to allow modification of existing 2D wire bondable devices into embeddable die formats with coarser pitches for relaxed die placement requirements with resultant gains in die placement speed. Additionally, cost effective wafer thinning and stress relieving down to die thicknesses of 100 microns and below are key requirements that cannot be overlooked.
This paper will provide an overview of leading embedded die technologies and the infrastructure that is developing to support them. Die customization is a key element of future technology acceptance in this space. The impact of device I/O pitch on die placement accuracy requirements and placement speeds will be outlined and the positive impact of wafer level redistribution on overall process complexity and cost will be outlined.
Keywords: 3D Packaging, Embedded Die, Build Up Printed Circuit Boards, Embedded Passives.
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