IWLPC (Wafer-Level Packaging) Conference Proceedings


INFRASTRUCTURE BUILDING FOR EMBEDDED DIE PRINTED WIRING BOARD APPLICATIONS

Authors: Theodore G. Tessier, et al.
Company: FlipChip International, LLC
Date Published: 10/13/2008   Conference: IWLPC (Wafer-Level Packaging)


Abstract: Embedded die technologies are emerging as attractive packaging alternatives for higher integration density, low profile packaging applications. A robust infrastructure to support embedded die packaging, driven by highly influential end-users including increased availability of Know Good Die (KGD), critical progress in large panel precision die placement and build up printed wiring board capabilities. The Hiding Dies program over the past 5 years has led a concerted consortial effort in Europe focused on enabling embedded die technologies. FCI has been quietly working behind the scenes to support this effort.

Beginning in 2009, high volume deployment of these technologies is expected to begin. A key part of this developing supply chain relates to modification and standardization of integrated circuits, integrated passives and other device technologies for embedding. Wafer level redistribution has been demonstrated to be a very cost-effective approach to allow modification of existing 2D wire bondable devices into embeddable die formats with coarser pitches for relaxed die placement requirements with resultant gains in die placement speed. Additionally, cost effective wafer thinning and stress relieving down to die thicknesses of 100 microns and below are key requirements that cannot be overlooked.

This paper will provide an overview of leading embedded die technologies and the infrastructure that is developing to support them. Die customization is a key element of future technology acceptance in this space. The impact of device I/O pitch on die placement accuracy requirements and placement speeds will be outlined and the positive impact of wafer level redistribution on overall process complexity and cost will be outlined.

Keywords: 3D Packaging, Embedded Die, Build Up Printed Circuit Boards, Embedded Passives.



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