IWLPC (Wafer-Level Packaging) Conference Proceedings


Authors: Eugene A. Stout, et al.
Company: FlipChip International, LLC; ENGENT, Inc.; and Auburn University
Date Published: 10/13/2008   Conference: IWLPC (Wafer-Level Packaging)

Abstract: As the move to higher performance and smaller components continues, interest in 3D packaging has moved to the forefront of electronic packaging. Current 3D packaging and stackable array packaging structures involve a mix of high density circuit boards with stacked ICs using wirebond interconnection and stackable array packaging structures. With advances in wafer thinning technology, 3D packaging now provides a robust platform for achieving high levels of integration, small package footprints, and thin package profiles. For emerging applications, further component miniaturization with the added benefit of 3D integration can be realized by Face to Face bonding of fine pitch flip chip components and low profile passives onto a redistribution layer of another silicon component (a wafer level chip scale package – WLCSP). This paper, the second in an ongoing series of publications will present a new low cost 3D WLCSP technology that leverages the existing infrastructures of wafer level packaging and high volume flip chip assembly. This paper focuses on wafer level design rules, assembly requirements and demonstrated reliability capabilities for this emerging technology.

Keywords: 3D Packaging, WLCSP, flip chip on silicon, wafer level fabrication, wafer level assembly

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