IWLPC (Wafer-Level Packaging) Conference Proceedings


3D WAFER LEVEL PACKAGING TECHNOLOGY FOR CIS APPLICATIONS

Author: Marc Robinson
Company: Vertical Circuits, Inc.
Date Published: 10/13/2008   Conference: IWLPC (Wafer-Level Packaging)


Abstract: Vertical Circuits Inc. has previously introduced the ViP™ Process which utilizes a conductive polymer interconnect to deliver low cost stacked packaging for both the DRAM and Flash Memory markets. More recently the authors have focused on the unique challenges related to the packaging of CMOS Image Sensors (CIS). CMOS Image Sensors have been gaining on conventional CCD Image Sensors especially in the cellular and hand-held markets due to recent performance improvements and lower cost to manufacture. The challenge of packaging such devices have hereto for focused on labor intensive plating technologies. The authors have found that the general adaptability of the digital dispensing process and the polymer interconnect generates a number of practical constructions towards the goal of a lower cost, high quality, CIS package technology. This paper will examine the benefits and challenges of applying conductive polymer interconnect technology to the packaging of these CIS devices.

Keywords: CMOS image sensor, conductive polymer, conformal coating, parylene, chip-scale package, memory, electronic packaging, semiconductor assembly



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