IWLPC (Wafer-Level Packaging) Conference Proceedings


INNOVATIVE FRONT TO BACK ALIGNMENT TECHNOLOGY FOR MEETING 3D PACKAGING REQUIREMENTS OF LEADING EDGE CONSUMER PRODUCTS

Authors: Manish Ranjan, Emily True, and Andrew M. Hawryluk
Company: Ultratech Inc.
Date Published: 10/13/2008   Conference: IWLPC (Wafer-Level Packaging)


Abstract: Miniaturization trends in consumer electronic devices have placed stringent manufacturing requirements for all process sequences in device fabrication. A number of new technologies are being developed to support increasing packaging density requirements. Three dimensional packaging technologies have gained increased acceptance for meeting the packaging requirements of devices such as CMOS image sensors. These advanced system in package (SiP) techniques require through silicon vias (TSV) to allow very high density vertical interchip wiring of multiple device stacks. Lithography techniques utilizing dual side alignment technology is one of the preferred methods for creation of these through silicon via structures. This feature has received wide spread acceptance from most customers involved in 3D packaging technology.

An innovative front to back alignment technology utilizing front side IR (infra red) approach for the dual side alignment process step is developed. The use of this approach allows customers with flexibility regarding target placement location. This feature is designed to achieve front-to-back overlay of less than 2 µm (mean + 3s) over a full 300 mm wafer. The primary development concept decisions concentrated on illumination wavelength, illumination source type, image sensor type, and optical design.

It is anticipated that the dual side alignment feature will be a key technology enabler for customers requiring through silicon via for 3D packaging and system in package applications.

Key Words: Through Silicon Via, Dual-side alignment, back-to-front alignment, system in package, wafer level packaging



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