IWLPC (Wafer-Level Packaging) Conference Proceedings


Author: Leslie M. Lea
Company: Surface Technology Systems
Date Published: 10/13/2008   Conference: IWLPC (Wafer-Level Packaging)

Abstract: Deep Reactive Ion Etching has become firmly established as a commercial technique for forming MEMS devices. Over the last decade, development work has led to increases in silicon etch rate of an order of magnitude while requirements for etch depth uniformity and profile control have become more stringent as the wafer size has increased from 3 inch up to 200 mm.

Recently interest has grown in the application of the DRIE technique to the formation of Through Silicon Vias (TSVs), which after metallization can be used to provide interconnections between stacked die of either the same type e.g. memory, or different types, for 3D System in Package (3D-SiP) applications. For wide commercial adoption of TSVs for interconnects the processes involved in their formation and filling must be very repeatable and reliable, enabling cost effective application on a production scale. The application of innovative technology to plasma processing equipment and the intensive development of the processes for packaging applications have significantly advanced etch capabilities in recent months. Commercially significant etch rates, in some cases exceeding 20 µm/ minute, can be achieved for via sizes of immediate interest, while excellent etch depth uniformity and profile control can be maintained over 300 mm wafers.

Keywords: Through Silicon Vias, Deep Reactive Ion Etching, high etch rate, interconnects

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