IWLPC (Wafer-Level Packaging) Conference Proceedings


Author: Rick Lathrop
Company: Heraeus Contact Materials Division
Date Published: 10/13/2008   Conference: IWLPC (Wafer-Level Packaging)

Abstract: Fine solder powder paste applications continue to grow as a cost effective solution to many semiconductor packaging needs. Applications for solder paste continue to evolve from the standard SMT market to the semiconductor backend. This paper describes capability and process details for wafer bumping, substrate bumping, Solder on Pad, BGA ball attach and System in Package applications. For wafer bumping, quantitative bump height data, demonstrates print process, stencil design and powder size effects. For Solder on Pad, stencil design and pad finish effects are discovered. For BGA ball attach, the ability to reduce final package coplanarity is disclosed using solder paste. For System in Package guidelines for paste printing 01005 chips is discussed. Quantitative data on material printability, dip-ability and pin transfer efficiency are covered in detail. Guidelines for suitable powder sizes for various applications are provided. Powder types from 5 through 8 are described and compared for various application processes as well as stencil and pin transfer tool designs. New areas of 3D packaging such as Package on Package utilizing dippable solder paste formulations are revealed.

KEY WORDS Solder paste, wafer bumping, SoP, BGA, PoP

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