IWLPC (Wafer-Level Packaging) Conference Proceedings


VIAS LAST TECHNOLOGY FOR CMOS IMAGE SENSORS: PRESENTATION OF DESIGN RULES AND TECHNOLOGY

Authors: David Henry, et al.
Company: CEA-LETI, MINATEC
Date Published: 10/13/2008   Conference: IWLPC (Wafer-Level Packaging)


Abstract: In this paper a low temperature ‘via-last’ technology will be presented. This technology has been especially developed for CMOS image sensors wafer level packaging. In the first part of this paper, the design of the TSV will be presented and a first approach of a design rule definition for TSV will be introduced. The alignment strategy will be also presented, and specific patterns to succeed front side to back side alignment will be described. In a second part the steps of the Through Silicon Vias (TSV) technology will be presented: glass wafer carrier bonding onto the silicon substrate, silicon thinning and backside technology including specific steps like double side lithography, silicon deep etching, silicon side wall insulation, vias metallization and final bumping. A special focus will be done on this paper on the TSV metallization step and especially on the chemical seed layer etching. A study has been achieved in this project in order to optimize this part of the process and the results will be shown. Then, morphological and electrical characterizations of the via-last technology will be presented and discussed. Finally, a picture obtained with the TSV CMOS Image Sensor (TSV CIS) will be shown.

Key words: Through Silicon Vias (TSV) – CMOS image sensors (CIS) - Advanced packaging – Wafer level technologies – Design rules – Wet etching



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