IWLPC (Wafer-Level Packaging) Conference Proceedings


3D CHIP PACKAGING FOR CLASS I MEDICAL DEVICES

Authors: John Dzarnoski, Ph.D. and Doug Link
Company: Starkey Laboratories
Date Published: 10/13/2008   Conference: IWLPC (Wafer-Level Packaging)


Abstract: There has been enormous worldwide effort to increase the volumetric efficiency of electronic packaging. Much of this effort has been driven by the telecommunications industry that has succeeded in reducing cell phone size while simultaneously increasing functionality. The hearing aid business has always had the need to use extremely small electronic packaging because hearing aids pack electronics into the ear canal. The industry trend is to put more memory, more signal processing capability and more wireless capability into hearing aids to increase functionality and to improve performance.

This paper will examine the history of 3D electronics packaging at Starkey. The challenges and drivers for each technology step will be discussed. Various issues will be examined including: available ASIC technologies, impact of chip metallization, solder interconnect temperature hierarchy, overcoming routing design limits, use of embedded passives, mixed wire bonded and flip chip attached die, and materials limitations. The following technology changes will be examined along with their impact on device packaging: move from analog to digital devices, benefits realized utilizing flip chip attach, chip stacking, use of conductive epoxy instead of solder, migration to stacked ceramic interconnect layers using vertical interconnect channels, and the incorporation of RF devices.

Key words: Isotropic conductive adhesive, Chip-on-flip-chip (COFC), Vertical Interconnect (VIC), Multi-chip module (MCM), System in a Package (SIP) and Heterogeneous chip integration.



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