IWLPC (Wafer-Level Packaging) Conference Proceedings


LITHOGRAPHIC CHALLENGES AND SOLUTIONS FOR 3D INTERCONNECT

Authors: Keith Cooper, et al.
Company: SUSS Microtec
Date Published: 10/13/2008   Conference: IWLPC (Wafer-Level Packaging)


Abstract: In order to integrate higher levels of functionality within a package, designers have employed creative strategies wherein multiple chip sizes, types or even materials have been combined into a single unit. Joining heterogeneous chip types such as optical, mechanical, and switching circuits has even been pursued to fabricate highly complex packages such as image sensors, biological or chemical sensing devices.

In the effort to create this new generation of advanced devices, designers have increasingly turned to the vertical dimension to increase the density and minimize the space, weight and power consumption. Chip stacking, through-silicon vias (TSV’s) and other vertical integration strategies have led to an increase in the Z dimension, which has created a new set of challenges for process engineers. Among these challenges are the needs to coat, pattern and etch structures which may have tens or even hundreds of microns in height. This paper will explore some of the lithographic challenges associated with 3D interconnection technology, where use of the vertical dimension has necessitated new methods of conformally coating high topography, new imaging techniques to align various masking levels to the underlying patterns, and new exposure techniques to accomplish high fidelity patterning over such high structures.

Keywords: lithography, photoresist, conformal coatings, 3D Integration and Packaging, exposure



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