Surface Mount International Conference Proceedings


APPLICATION REALITIES OF CHIP SCALE PACKAGING

Author: Ronald Malfatt
Company: IBM Microelectronics
Date Published: 9/10/1996   Conference: Surface Mount International


Abstract: Chip Scale Packaging (CSP) is being considered by many as the future area array solution to satisfy the evolutionary growth in I/O densities that are demanded by ever increasing levels of silicon performance and integration. Numerous CSP developers tout claims of miniaturization, improved performance and reduction of package contribution to overall module cost, attributes highly desirable in any new packaging technology. Proponents state that realization of these goals in the CSP form factor is in line with an existing or soon to be existing supporting industry infrastructure. CSP critics and technology analysts question this assertion. Thus, several key technology and business issues must be addressed before it becomes clear if CSP can indeed serve as the universal packaging solution of the future, ie. for I/O ranges from a few to over 1000, and in markets ranging from low-cost consumer through high-end data processing applications. This paper will discuss the application boundaries within which CSP is a viable solution as well as addressing the major limiters to CSP’S broad and practical utilization. In addition we will explore the interactions between area array package I/O pitch, card groundrules and wireability.



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