Pan Pacific Symposium Conference Proceedings


PROCESS AND ASSEMBLY METHODS FOR INCREASED YIELD OF PACKAGE ON PACKAGE DEVICES

Authors: Brian Toleno, Ph.D. and Dan Maslyk
Company: Henkel Corporation
Date Published: 1/24/2008   Conference: Pan Pacific Symposium


Abstract: Increased functionality and smaller devices are significant drivers in innovative packaging designs. One of the newer package types to be introduced into the market place in the past few years is the package on package (PoP) devices. While packaging houses have been stacking die within memory and other packages for several years, this methodology is subject to known good die issues and other challenges that can drive up cost. In addition, this limits the designer on what functionality can be “stacked”, since these come packaged together in a single unit. Stacking packages offers significant advantages from a design standpoint. As long as the pad designs are compatible, different device types can be stacked allowing for more versatility in the design and the assembly. On the other hand, assembling these devices on a standard SMT line can present challenges. Some assemblers purchase or acquire these devices preassembled, but the trend is towards assembling these on the printed circuit board (PCB) during a standard SMT process. Once solder paste is printed on the PCB and the first level component is placed, the attachment methodology of the second level device is not as clear. Therefore, in order to reflow these all in one pass alternative measures need to be investigated.

In this paper we compare the process conditions and yield achieved when assembling package on package devices utilizing different materials and methodologies. In all cases the devices were Pb-free devices with solder paste used for the bottom package. The material and process and materials were varied for the top package. The materials used for the top package assembly included tacky flux, solder paste, and an epoxy flux system. Once assembled the devices were tested for electrical yield, solder joint metallurgy integrity, and standoff height.

Key words: Package on Package, PoP, SMT Assembly



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