Pan Pacific Symposium Conference Proceedings


Authors: Eric Mounier, Ph.D., Jérôme Baron, and Jean-Christophe Eloy
Company: Yole Développement
Date Published: 1/24/2008   Conference: Pan Pacific Symposium

Abstract: Stacking chips in 3D with TSVs (“Through-Si Vias”) as interconnects is today a “hot” new advanced packaging technology platform for memories, CMOS imagers and MEMS. Although the technical challenges for 3D ICs are close to be overcome, the cost of the technology is still a major hurdle. TSVs have many advantages: smaller form factor, better performance … but they also have to face many competing stacking technologies (PoP, PiP) for which competing interconnect technology such as wire bonding is very low cost.

Moreover, there are numerous market drivers for TSVs, depending upon the final applications. We will review them in this article. We have also developed an internal tool which can be used for semiconductor wafer cost calculations. We used it for cost modeling for TSV and this article shows our results.

Key words: TSV, COO, 3D packaging

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