Author: R. Joshi Company: National Semiconductor Corp. Date Published: 9/10/1996
Surface Mount International
Abstract: The recent trends in miniaturization have led to a need for higher I/O packages, yet with smaller form factors. The electronics industry has responded with several versions of small footprint packages. One such concept is the chip scale package. Currently the cost of such a package is very high, partly from the lack of an infrastructure to support it. A lower cost, plastic chip carrier approach is proposed here. Although the plastic chip carrier may not always fit the exact definition of a chip scale package (i.e. the package area of less than 1.2 times the die area), it does have a smaller footprint as compared to conventional surface mount leaded packages. The plastic chip carrier may also have a lower cost structure associated with it due to its simplified assembly process flow. In addition, the chip carrier design discussed here would not have the coplanarity issues associated with conventional surface mount packages. This paper will discuss the proposed constructional details of this package. Issues such as material selection, reliability and performance of this package are important and will be discussed in later evaluations.