Symposium Conference Proceedings


Authors: Klaus Ruhmer and Eric Laine, et al.
Date Published: 6/21/2007   Conference: Symposium

Abstract: Microelectronic packaging continues to migrate from wire bond to flip chip interconnect to meet requirements for improved electrical performance, reduced size and weight. For wafer bumping, solder electroplating is commonly employed, especially for fine pitch applications. Wafer level chip scale packaging (WLCSP) typically utilizes solder sphere placement technology to manufacture the bumps. C4NP (Controlled Collapse Chip Connection New Process) has proven to be suitable for a broad range of solder bump pitches, encompassing FCiP to CSP bump dimensions. As the industry migrates to 300mm wafer processing and leadfree flip chip interconnect, C4NP is establishing itself as a viable solder bumping alternative.

The under bump metallurgy (UBM) structure is a key component of any solder interconnect system. The UBM typically provides three functions: adhesion to underlying dielectric and metal, barrier to protect the silicon circuitry, and a solder wettable surface. For lead-free bumps, the barrier layer is key to reliability due to their higher Sn content. A common barrier layer used in the industry is electroplated nickel. This layer provides good protection from degradation of the silicon metallurgy by tin rich lead free solders. C4NP provides an opportunity to eliminate electroplating, and its associated costs for plating chemistry, analysis, supply and waste treatment.

This paper analyzes two alternative UBM structures: sputtered TiW/Ni and electroless Ni/immersion Au (ENIG), with and without Pd. Wafers were fabricated with these UBM structures, solder applied with C4NP, and chip level stressing performed to determine the robustness of these alternative stack-ups. Analysis of these structures following multiple reflows and thermal cycling is presented.

C4NP is a novel solder bumping technology developed by IBM which addresses the limitations of existing bumping technologies by enabling low-cost, fine pitch bumping using a variety of lead-free solder alloys. It is a solder transfer technology where molten solder is injected into prefabricated and reusable glass molds. The glass mold contains etched cavities which mirror the bump pattern on the wafer. The filled mold is inspected prior to solder transfer to the wafer to ensure high final yields. Filled mold and wafer are brought into close proximity/soft contact at reflow temperature and solder bumps are transferred onto the entire 300mm (or smaller) wafer in a single process step without the complexities associated with liquid flux. C4NP technology is capable of fine pitch bumping while offering the same alloy selection flexibility as solder paste printing. The simplicity of the process makes it a low cost, high yield and fast cycle time solution for both, fine-pitch FCiP as well as WLCSP bumping applications.

The data in this paper is provided by the analytical laboratory at Fraunhofer Institute, IZM, Berlin, Germany. UBM formation was done at NEXX Systems, Billerica, MA and Fraunhofer IZM. Wafer bumping was done using the C4NP process at the IBM Hudson Valley Research Park.

Members download articles for free:

Not a member yet?

What else do you get when you join SMTA? Read about all of the benefits that go along with membership.

Notice: Sharing of articles is restricted to just your immediate work group. Downloaded papers should not be stored on an external network or shared on the internet.


SMTA Headquarters
6600 City West Parkway, Suite 300
Eden Prairie, MN 55344 USA

Phone +1 952.920.7682
Fax +1 952.926.1819