SMTA International Conference Proceedings


LOW PROFILE NAND FLASH STACKED PACKAGE-ON-PACKAGE

Author: Vern Solberg
Company: Tessera, Inc.
Date Published: 10/11/2007   Conference: SMTA International


Abstract: The motivation for developing higher density IC packaging continues to be the market and the consumers’ expectation that each new generation of products furnish greater functionality. The miniature IC package evolution began with the development of chip-scale and die-size package technology. These miniature IC package innovations proved ideal for portable and hand-held electronic applications. To address the need for even more functionality without increasing their products size, a number of companies have adapted various forms of multiple-die 3D packaging.

A majority of these early multiple function devices relied on the sequential stacking of die elements onto a single substrate interposer. The die-to-substrate interface was generally made using a conventional wire-bond process, but, because the wire-bonding of multiple tiers of uncased die is rather specialized and the die used may have had relatively poor wafer level yields or the overall manufacturing yield of the stacked-die packaged devices have not always met acceptable levels.

The material developed for this SMTA program will outline current expectations for multiple function packaging for hand-held and portable electronic applications and consider a number of mixed memory and mixed function variations using the vertically stacked µPILR™ package-on-package technology. The information presented in this paper will focus on the on a new substrate fabrication process developed to improve both IC package density and circuit routing efficiency. In addition, the basic package assembly methodology will be described with a detailed overview of the development and qualification test program for a four layer stacked NAND FLASH product.

Key words: µPILR, CSP, PoP, FLASH Memory



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