Surface Mount International Conference Proceedings


CRITICAL ISSUES WITH CHIP SCALE PACKAGES (CSPS)

Author: Steve Greathouse
Company: Intel Corporation
Date Published: 9/10/1996   Conference: Surface Mount International


Abstract: In an amazingly short time for packaging trends, Chip Scale Package options have exploded into the electronic packaging world. Almost without exception, no packaging option has garnered as much time and space in publications and symposiums in such a short time since a new concept has been announced. Whole conferences are now dedicated to the discussion of CSPS. To be properly called a Chip Scale Package or CSP, (or Chip Size Packages if they are the same size as the die it contains), the finished package needs to conform to the definition of being between 1 to 1.2 times the perimeter of the die the package contains. In some circles, the definition also includes any type of package that has a maximum area of 1.5 times the size of the die. The goal of a CSP is to provide the benefits of the small size and performance of bare die or a flip chip, and yet have the advantages, convenience, standards, and die protection of a packaged device. Many authors have grouped CSP types into the following 5 categories, usually segregated by the method of construction. (See figure #1 for further information). 1) Interposers with Flex circuit interconnect, 2) Interposers with Rigid Substrates, 3) Customized lead frame (LOC), 4) Miniature Molded packages. 5) Wafer level assembly packages. Each construction method and type has their respective advantages and disadvantages that have been discussed in detail in other papers and presentations, l therefore, no further effort to duplicate their work will be undertaken here. Instead, a deeper look into the issues and concerns with CSPS will be presented.



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