VOID FORMATION STUDY OF HIGH I/O DENSITY AND FINE PITCH FLIP CHIP IN PACKAGE USING NO-FLOW UNDERFILLAuthors: Sangil Lee, Daniel F. Baldwin, Ph.D., Raj Master, Ph.D., and Srinivasan Parthasarathy
Company: Georgia Institute of Technology and Advanced Micro Devices
Date Published: 10/11/2007 Conference: SMTA International
The application of no-flow underfills for FCIP having high I/O density (over 3000 I/O), fine pitch (down to 150 µm), full area array interconnect structures creates a challenge for interconnect yield. A typical FCIP interconnect system comprised of high lead solder bumps with eutectic lead-tin solder interconnects was applied to FCIP test vehicles. Reflow design parameters including higher ramp rates and higher time above liquidous were selected in order to achieve robust interconnects without disruption of the FCIP interconnect structure. However, these reflow conditions have the side effect of causing a large amount of voids in FCIP.
The larger void content of these assemblies may result in decrease reliability. Therefore, it is essential to investigate the plausible source of void formation, specifically outgassing voids, in order to maximize yield and reliability. This paper presents a systematic investigation into the plausible causes of void formation in FCIP through the use of structured experimentation which was designed using four types of test vehicles, leading to a better understanding of the void formation in FCIP.
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