SMTA International Conference Proceedings


CHALLENGES IN SUB-MICRON TEST

Author: Alek Jaworski
Company: Jabil
Date Published: 10/11/2007   Conference: SMTA International


Abstract: This paper provides an overview of Built-In Self Test (BIST) methods that are currently used in the board manufacturing test process. In addition it explores how these DFT features can be used to improve the testing, analysis and debugging of highly integrated, high speed boards. Application of data mining BIST failure data to drive manufacturing process and component quality improvements is also presented.

Silicon integration and complexity continues to increase as do clock speeds and logic density. This increasing complexity is presenting new problems for board assembly manufacturers tasked with assembling and testing products that contain these highly complex silicon devices. Automated optical inspection (AOI), X-ray inspection (AXI), and structural tests like Boundary Scan Test (BST) and In-Circuit Test (ICT) verify the bonding of the Integrated Circuits (IC) to the traces on the board. These inspection and test methods are effective at determining gross manufacturing errors, regardless of the type of technology being manufactured or the complexity of the IC.

Inspection and structural tests are effective at finding manufacturing defects but cannot guarantee that each assembly will perform to design specifications. Consequently Functional Verification Test (FVT), often in conjunction with Environmental Stress Screening (ESS), is a necessary process. These test methods can ensure both proper component function and interoperability between components that cannot be guaranteed by inspection or structural test. To enhance testability, Original Equipment Manufacturers (OEMs) and component manufacturers are incorporating Built-In Self Test (BIST) into VLSI components to enhance testability at FVT.



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