CHALLENGES IN SUB-MICRON TESTAuthor: Alek Jaworski
Date Published: 10/11/2007 Conference: SMTA International
Silicon integration and complexity continues to increase as do clock speeds and logic density. This increasing complexity is presenting new problems for board assembly manufacturers tasked with assembling and testing products that contain these highly complex silicon devices. Automated optical inspection (AOI), X-ray inspection (AXI), and structural tests like Boundary Scan Test (BST) and In-Circuit Test (ICT) verify the bonding of the Integrated Circuits (IC) to the traces on the board. These inspection and test methods are effective at determining gross manufacturing errors, regardless of the type of technology being manufactured or the complexity of the IC.
Inspection and structural tests are effective at finding manufacturing defects but cannot guarantee that each assembly will perform to design specifications. Consequently Functional Verification Test (FVT), often in conjunction with Environmental Stress Screening (ESS), is a necessary process. These test methods can ensure both proper component function and interoperability between components that cannot be guaranteed by inspection or structural test. To enhance testability, Original Equipment Manufacturers (OEMs) and component manufacturers are incorporating Built-In Self Test (BIST) into VLSI components to enhance testability at FVT.
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