KNOWN GOOD DIE VERSUS CHIP SIZE PACKAGE: OPTIONS, AVAILABILITY, MANUFACTURABILITY AND RELIABILITY
Author: Lany Gilg Company: MCC Date Published: 9/10/1996
Surface Mount International
Abstract: The increasing density, high speed performance and increased functionality of integrated circuit components are fueling demands for smaller sized, higher speed portable electronic systems. Designers are cutting size, delays and costs wherever possible. One area that offers attractive benefits for size reduction and performance improvement is in the IC package itself, either eliminating it altogether and attaching the bare IC chip directly to the board, or reducing the size to the point where it takes up very little more space than the IC itself, the recently defined chip size package. Traditionally, the integrated circuit (IC) package has provided a number of benefits for the electronics system assembler. It provides protection from harsh environments, especially humidity and contamination. Package sizes have been relatively large-scale, allowing ease of handling for manufacturing and assembly. The package provides a mechanism for thermal management, that is, a means to conduct heat generated by the IC away through the metal connections to the chip or to the backside (via thermal die attach). Electrical connection to the package leads is facilitated, and the package can be mounted temporarily in a socket for ease of testing or debugging. Increasingly, however, manufacturers of electronics systems are turning to two new approaches in IC packaging to solve size, weight and performance issues - Chip Size Packages (CSP) and Known Good Die (KGD). While each of these approaches offer solutions to some of the problems confronting OEMS in the search for product differentiation, each approach introduces its own set of issues that must be addressed.