SMTA International Conference Proceedings


Authors: Sundar Sethuraman, Richard Coyle, Richard Popowich, and Peter Read
Company: Alcatel-Lucent and Solectron Corporation
Date Published: 10/11/2007   Conference: SMTA International

Abstract: The relationship between voiding and long term reliability in area array solder joints has been a topic of considerable controversy. Although there have been numerous investigations, a definitive correlation has not been established between process voiding and a degradation to long term solder fatigue life. Printed Circuit Board Assemblies (PCBAs) can be rejected based on the IPC guidelines for voiding but those guidelines are based more on geometric assumptions than test data. A recent IPC Pb free study concluded that voiding does not influence reliability, which is a fairly common opinion. Some studies have suggested that voids can arrest crack propagation and improve reliability. Conversely, studies of planar voiding indicate that reliability can be reduced in both mechanical testing and thermal cycling.

This work employs methods developed in a previous investigation to generate macrovoiding patterns that can be used to assess voiding and solder fatigue life. The test vehicle consists of a 0.5 mm pitch SnPb chip scale package (CSP) and blind microvia in pad board mounting. The voiding and void distributions are controlled through various combinations of surface mount reflow parameters and surface finish. Long term fatigue life is evaluated using typical IPC-9701 test conditions for accelerated temperature cycling (ATC). Voiding is characterized using automated Xray inspection and failed solder joints are examined with optical microscopy. The fundamental conclusion of the study is that voiding can reduce the interconnect fatigue reliability but that void location, not void size or volume fraction, has the primary impact on fatigue life.

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