SMTA International Conference Proceedings


THROUGH SILICON VIA INTERCONNECTION ENABLING 3D WAFER-LEVEL SIP

Authors: Lars Boettcher, Andreas Ostmann, Dionysios Manessis, and Herbert Reichl
Company: Fraunhofer Institute for Reliability and Microintegration (IZM)
Date Published: 10/11/2007   Conference: SMTA International


Abstract: High density packaging realized by 3D stacking is becoming more and more important for consumer electronics that combine more functions and higher memory capacity with significant size shrinkage. Three dimensional chip stacking with silicon through hole vertical connections provides the potentially best technology for a semiconductor system integration. Such a technology provides an interesting approach due to its shrinkage capability and signal transmission performance.

The realization of highly miniaturized System in Package (SiP) or thin stackable packages containing active and passive devices, the formation of 3-D interconnection patterns, making interconnection through the silicon wafer and connecting top to bottom, requires new or improved manufacturing technologies.

In this paper two different approaches for the realization of highly miniaturized packages will be presented. Both approaches are based on vacuum lamination and laser via and structuring technologies.

The first part describes the continuous development of a through silicon via interconnect approach which is based on the lamination of epoxy coated copper films (Resin Coated Copper - RCC). The goal of this technology is to realize chip size SiP, using highly flexible laser technology for the realization of the Through Silicon Via (TSV) interconnection in combination with a cost efficient lamination of dielectric films.

As a second technology, the embedding of silicon dies into polymer layers will be described also. This technology aims for the realization of ultra thin chip scale package or SiP. In order to realize such a package, the active dies will be embedded directly into RCC build up layers and laser micro via formation will be used to produce interconnects to chip pads and substrate.

In the result for both approaches, semiconductor chips are fully integrated into a flat substrate. If required, further layers can be applied or other components can be conventionally assembled on top.

Key words: 3D packaging, embedded chips, SiP, CSP, resin coated copper (RCC), vacuum lamination, laser drilling, Through Silicon Via



Members download articles for free:

Not a member yet?

What else do you get when you join SMTA? Read about all of the benefits that go along with membership.

Notice: Sharing of articles is restricted to just your immediate work group. Downloaded papers should not be stored on an external network or shared on the internet.


Back


SMTA Headquarters
6600 City West Parkway, Suite 300
Eden Prairie, MN 55344 USA

Phone +1 952.920.7682
Fax +1 952.926.1819