IWLPC (Wafer-Level Packaging) Conference Proceedings


WAFER PLATING USING A SINGLE CHAMBER, MULTI-METAL, BUMP PLATING TOOL

Authors: Steven Cho and Lee Levine
Company: Surfect Technologies, Inc
Date Published: 9/17/2007   Conference: IWLPC (Wafer-Level Packaging)


Abstract: By 2010 10% of the entire interconnect market will be produced by the flip chip process, with the largest segment being electroplated copper-solder bumps (25% CAGR).

Currently these interconnects are produced in multi-tank in-line plating facilities, but the capital equipment costs for this equipment are very high and represent a barrier to entry for smaller companies. A new single-chamber, multi-metal layer, plating computer has been designed to achieve both high plating rates and high quality bumps with a significantly lower equipment cost than conventional equipment. It has improved manufacturing flexibility, and easy programmability. Data from DOEs and beta site testing are provided.

Keywords: Flip chip, bump, plating, interconnection



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