IWLPC (Wafer-Level Packaging) Conference Proceedings


Author: Leslie Lea
Company: Surface Technology Systems plc,
Date Published: 9/17/2007   Conference: IWLPC (Wafer-Level Packaging)

Abstract: As device manufacture moves from the use of 200mm wafers to 300mm wafers, there is a requirement for the etching of features for Chip Scale Packaging (CSP) and vias for interconnects for System-in-Package (SiP), also to move to the larger wafer size. Deep Reactive Ion Etching (DRIE) has been developed in connection with the manufacture of MEMS devices such as pressure sensors, gyroscopes, optical switches and micro mirrors. It is an enabling technology that is very suitable for etching for example scribe channels for CSP and vias which after filling with metal can provide direct chip-to-chip connections that reduce the need for wire interconnects for SiP.

For MEMS applications the wafer size often used is 150mm with a move to 200mm only recently occurring for some devices. The economics of MEMS device manufacture is unlikely to justify the move to 300mm wafers for some years unless combined at wafer level with processing circuitry.

Results are presented of DRIE of features on 300mm wafers using the latest generation of plasma etch tool developed by STS primarily for WLP. Good uniformity of etch rate across wafer and accurate control of feature dimensions are shown, with etch rates similar to or beyond those previously obtained on 200mm wafers.

Keywords: Chip Scale Packaging, System in Package, Deep Reactive Ion Etching, 300 mm wafers, plasma etch

Members download articles for free:

Not a member yet?

What else do you get when you join SMTA? Read about all of the benefits that go along with membership.

Notice: Sharing of articles is restricted to just your immediate work group. Downloaded papers should not be stored on an external network or shared on the internet.


SMTA Headquarters
6600 City West Parkway, Suite 300
Eden Prairie, MN 55344 USA

Phone +1 952.920.7682
Fax +1 952.926.1819