THE COMING PARADIGM SHIFT IN PACKAGINGAuthors: Ken Gilleo, Ph.D.
Company: ET-Trends LLC
Date Published: 9/17/2007 Conference: IWLPC (Wafer-Level Packaging)
Semiconductor memory modules and other solid-state products have used 3D chip stacking for more than a decade. One popular scheme is to stack decreasingly smaller chips on top of one another to form a “pyramid” (aka, “wedding cake”). The pyramid package taps into the infrastructure to use wire bonding and other standard processes, hence its popularity. But this one-chip-at-a-time, volume-wasting method does not produce an optimal 3D package. The added length of bonding wires also reduces performance. But the pyramid design, though not optimal, may enjoy longevity because it does not require radically different methods.
But there is an alternative that can deliver the ultimate in density and performance. A number of researchers have been diligently working on through-wafer connections, or Through-Silicon Vias (TSV), but somewhat quietly until now. The TSV concept is elegant in its simplicity, but technically challenging. This paper will discuss TSV formation, filling, bonding, and final packaging from the wafer level perspective. We will also assess the chances for TSV success, potential products, and the impact on supply chain dynamics that may dramatically change if the quiet revolution turns up the volume.
Keywords: TSV, 3D package, stacked package
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