IWLPC (Wafer-Level Packaging) Conference Proceedings


CHIP PACKAGING 2.0 – USER DEFINABLE CHIP PINOUT PACKAGING FOR OPTIMIZED PC BOARD DESIGN

Author: Martin Hart
Company: Mirror Semiconductor, Inc.
Date Published: 9/17/2007   Conference: IWLPC (Wafer-Level Packaging)


Abstract: System designers have an ongoing need to optimize board-level designs. The cost to spin new chips from scratch is prohibitive in today’s business environment. Legacy chips are routinely thrown “over the wall” to board designers, often years after the chips were designed. In the current world, legacy chipmakers have limited interest to talk with board designers. Board designers are constrained from developing fully optimal boards in the current so-called “Chip Packaging 1.0” environment and there is a clear need to change.

In the proposed new “Chip Packaging 2.0” environment, board designers start with off-the-shelf legacy die (wafer) and use suitable EDA software to re-map the chip’s pinout (without altering the performance of the silicon) while simultaneously optimizing the board design. The EDA software would create a bonding schedule for delivery via the internet or by conventional means to wirebonding machines for assembly.

This paper poses the question what if board designers were empowered to re-map legacy chip package pinouts, in order to design optimum boards in a Chip Packaging 2.0 world?

Prevailing conventional wisdom in today’s Chip Packaging 1.0 world presumes that only the chip design team is qualified to define IC package pinouts. That argument is compelling, since the chip design team is most familiar with the silicon chip, and therefore most qualified to determine the packaging and pinout. Since no communications channel exists between the Chip Packaging 1.0 silicon design team and the board designer, boards are chronically constrained from being fully optimized.

For purpose of this paper, an “optimized” or “optimal” board shall be defined as being the smallest in size, with shortest copper routing, fewest inner-layers operating at the highest performance, and potentially having the quickest development time to market.

Keywords: chip packaging 2.0, mirrored pinout, reversed pinout, UDPo



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