IWLPC (Wafer-Level Packaging) Conference Proceedings


Authors: Shari Farrens, Ph.D.
Company: SUSS MicroTec
Date Published: 9/17/2007   Conference: IWLPC (Wafer-Level Packaging)

Abstract: Vertical integration of devices at wafer and chip level is maturing into high volume production. First products will include memories for mobile applications, image sensors and various MEMS sensors for consumer applications(1). Wafer bonding techniques are arguably one of the keystone processes that will facilitate the successful transition from traditional two dimensional scaling to high performance vertically integrated materials and technologies. Integration of product lines and heterogeneous materials involves a complex balancing act of thermal management, uniform applied force, and environmental controls. This has raised the bar for the performance metrics for commercial bonding equipment.

Most vertically integrated devices are also incorporating through silicon vias that not only allow for final packaging advances but complete the electrical connections between the stacked die and wafers. Metal bonding schemes are the obvious choice for electrical connections and also have the advantage of creating hermetic seals with reduced dimensions. The common metal seals used in 3D stacking are the Cu-Cu diffusion processes and eutectic alloys.

Simultaneously, the scaling advantages that are afforded by 3D integrated architectures are increasing the demands for overlay accuracy in bond alignment. A general rule of thumb has been that the aligner accounts for 0.1um of shift, the wafer fixture accounts for 0.1um of shift, and the bonder accounts for 0.1 um of shift from ideal or perfect overlay accuracy. This leaves little budget for thermal expansion differences, lithographic run out, or human error. This illustrates the pressures placed on the equipment suppliers to meet deep submicron specifications for stacked memory.

Keywords: Metal bonding, wafer level integration, 3D Integration, eutectic bonding, Cu-Cu bonding.

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