A RELIABLE WAFER-LEVEL CHIP SCALE PACKAGE (WLCSP) TECHNOLOGYAuthors: Umesh Sharma and Philip Holland et al.
Company: California Micro Devices, Inc. and Ozen Engineering, Inc.
Date Published: 9/17/2007 Conference: IWLPC (Wafer-Level Packaging)
In this paper, we systematically analyze the problem of passivation cracking and present a WLCSP process that is resistant to cracking during solder flow and subsequent multiple reflow steps. ANSYS thermo-mechanical finite element modeling software is used to model the WLCSP structure and process flow to evaluate stress and deformation at various points across the device structure. Contour plots clearly highlight the high stress regions and pinpoint the potential failure region. The use of ANSYS software in optimizing process parameters, and predicting reliability is presented. The experimental results confirm our simulation results and we conclude by presenting an optimized process that is resistant to passivation cracking and resulting failures.
Keywords: WLCSP, passivation cracks, re-passivation, ANSYS, simulations
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