IWLPC (Wafer-Level Packaging) Conference Proceedings


Authors: Larry Wang and Violet Evans et al.
Company: LORD Corporation and NSF Center for Advanced Vehicle Electronics (CAVE)
Date Published: 9/17/2007   Conference: IWLPC (Wafer-Level Packaging)

Abstract: Flip Chip (FC) and Wafer Level Packaging (WLP) are two of the fastest growing segments in the IC packaging industry due to their design advantages. Both of them impose significant new demands on underfill encapsulation materials. Specifically, the flip chip devices are moving towards smaller stand-off gaps, finer bump pitches, and denser area array interconnects. Each of these trends contributes to making the underfilling process more difficult for the current underfill technologies and in some cases unworkable. On the other hand, shifting the underfill process to the wafer level offers several benefits, but wafer level applied underfills face a different set of obstacles that have to be overcome before obtaining wide market acceptance.

Separately, safety and health concerns along with regulatory limitations on anhydrides used in traditional underfills also force material suppliers to explore different chemistries and technologies for underfill products. In all cases, the reliability requirements and standards on the packaged devices must not be compromised.

In the meantime, the worldwide initiative to switch from eutectic solder to lead free alloys makes the situation even worse due to the higher reflow temperatures and unfavorable characteristics of lead free solders. Lead containing solders have been employed as an interconnecting and surface coating material in many applications for decades. The two driving forces that affect the present and future requirements of solders for electronic and microelectronic applications are, first, the increased demands on the level of performance due to the increased density and complexity of circuitry and secondly, concern about the toxicity and health hazards of lead. The second concern has led to government legislation and regulations that have continued to impact the future of lead usage. Extensive literature on lead-free solders has been published in the last decade. A growing area of interest is in lead-free solders for flip chip interconnects. Flip chip interconnections are the electrical and mechanical connections between the semiconductor integrated circuit and the package. These interconnects are formed on the periphery or in an area array on the active surface of a die. Flip chip interconnect bumps are smaller (of the order of 100 µm diameter) than other surface mount joints and bump pitches are very fine at 100-150 µm or below. The solder joints must withstand board level reflow environments compatible with joining organic substrates that, again, have a maximum reflow temperature of 260°C. The lead-free solder must meet these requirements and perform at, or above, the level of performance of the eutectic tin-lead solder alloy. Historically, the underfill has been taking the burden to provide such needed protection of solder bumps (eutectic or lead-free). That is to say, all the challenges aforementioned are now effectively transferred onto underfill materials.

Aside from above, integrated circuits are moving towards higher power density with increased constraint on device size and available space within a package. The resulting heat is becoming more intense and heat dissipation is often a critical consideration when designing a flip chip device. We are pioneering the development of a unique, thermally conductive underfill that is used to conduct heat from the chip to the substrate. This is especially beneficial when flip chip devices have space limitations that exclude conventional thermal interface materials applied to the top.

This paper describes the key challenges in developing underfill technologies imposed by the package geometries (smaller gaps and denser interconnects) and performance requirements (faster flow, better reliability performance and thermal conductivity). These new demands on underfill will require polymeric materials with improved chemistries and fillers with specially selected size, size distribution and morphology. In particular, we will discuss the design, development and characterization of two non-anhydride underfills with low viscosity, small particle size fillers, fast flow and high reliability. These properties are essential in the underfill for encapsulation of small to large die with narrow stand-off heights between the die and the substrate. Board level reliability results using lead-free solder joints will also be discussed, including thermal cycling, thermal shock, and humidity testing, along with confocal scanning acoustic microscopy (CSAM), scanning electronic microscopy (SEM) and X-ray images.

Current work has shown that the two underfills presented here have excellent processing properties with fast flow, uniform flow fronts, and non-settling of filler particles. The assembled (cured) flip chip devices also showed uniform filler distribution, high adhesion, and excellent reliability after 3000 cycles in air-to-air thermal cycling (AATC), Underfill B also showed the expected lower Theta-JA temperature in flip chip device compared to a conventional underfill, indicating the desired heat dissipation effect.

Keywords: flip chip, lead-free, underfill, reliability, thermal conductivity

Members download articles for free:

Not a member yet?

What else do you get when you join SMTA? Read about all of the benefits that go along with membership.

Notice: Sharing of articles is restricted to just your immediate work group. Downloaded papers should not be stored on an external network or shared on the internet.


SMTA Headquarters
6600 City West Parkway, Suite 300
Eden Prairie, MN 55344 USA

Phone +1 952.920.7682
Fax +1 952.926.1819