IWLPC (Wafer-Level Packaging) Conference Proceedings


Authors: Daniel Baldwin and Michael Colella
Company: Engent, Inc. and Intel Corporation
Date Published: 9/17/2007   Conference: IWLPC (Wafer-Level Packaging)

Abstract: The formation of underfill voids is an area of concern in the low cost, high throughput, or “no-flow” flip chip assembly process. A novel hybrid process has been developed that combines a capillary underfill flow dynamic with no-flow fluxing underfills to result in near void-free assemblies. This new hybrid no-flow process is reviewed in this work. Systematic reliability testing has been conducted for the new hybrid process. The results presented in this paper compare conventional no flow underfill process with the new hybrid process. Flip chip test vehicles were assembled according to an optimal process developed for four commercially available no-flow underfills. Two reliability tests were used to evaluate the new process. Accelerated reliability tests performed included air/air thermal cycling and autoclave testing. The newly developed edge patterned hybrid no-flow process has resulted in near void-free assemblies capable of passing 2000 cycles without failure for the -40 to 125 °C thermal cycle reliability test. The results for this reliability testing is detailed. The new process has potential to avoid the problem of early solder extrusion into underfill voids during thermal and thermomechanical stressing of the assemblies. The overall reliability performance for the new process is exceptional relative to conventional no flow processing techniques.

Keywords: flip chip, reliability, no flow underfill

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