IWLPC (Wafer-Level Packaging) Conference Proceedings


Authors: Guilian Gao and Bel Haba et al.
Company: Tessera Inc. and Tessera Israel Inc.
Date Published: 9/17/2007   Conference: IWLPC (Wafer-Level Packaging)

Abstract: Wafer Level Packaging (WLP) holds promise for the small package form factor, low cost, high parallelism, minimal component handling and test and burn-in while in wafer form. However, solder joint fatigue due to stresses generated by the CTE mismatch between the die and the printed circuit board (PCB) has limited adoption of WLP to die smaller than 5mm x 5mm.

Tessera’s new compliant WLP technology greatly enhances thermal fatigue reliability. A compliant layer under the solder joints effectively minimizes thermo-mechanical stress between the die and the PCB. High reliability has been demonstrated on a 9mm x 14mm package. The prototype units exceeded 1600 cycles of temperature cycling from -40oC to 125oC. A compliant WLP package version with plated copper posts was also developed. This structure holds the promise to enable wafer level test and burn-in at a cost substantially lower than current WLBT technology, which requires expensive wafer contactors. Daisy chain continuity with wafers pressed directly against a test board has been demonstrated.

Key words: Compliant WLP, reliability, FEA, test, burn-in

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