IWLPC (Wafer-Level Packaging) Conference Proceedings


A PHOTOSENSITIVE, SPIN-APPLIED MASKING MATERIAL FOR THROUGH-SILICON VIA FORMATION FOR WAFER-LEVEL PACKAGING

Authors: Ramachandran K. Trichur and Xie Shao
Company: Brewer Science, Inc.
Date Published: 9/17/2007   Conference: IWLPC (Wafer-Level Packaging)


Abstract: In the realm of three-dimensional (3-D) integration, through-wafer interconnections using through-silicon vias (TSVs) for wafer-level 3-D integration and stackable IC packaging are receiving more attention because TSVs help to increase the interconnect density, decrease wire lengths, and save space. These effects lead to high performance, low power requirements, and smaller electronic gadgets.

TSVs are created mainly using dry-etch processes [1], [2], laser drilling [3], and wet-etch processes [4]. The dry-etch process provides fine-pitch and high-aspect-ratio via holes, while the wet-etch process provides an economic alternative through batch processing and is easier for subsequent metallization due to tapered via structure and smooth via surface along the [111] crystalline plane. Traditionally, silicon nitride deposited by plasma-enhanced chemical vapor deposition (PECVD) or low-pressure chemical vapor deposition (LPCVD) has been used as an etch mask during the wet-etch process using potassium hydroxide (KOH) or tetramethylammonium hydroxide (TMAH). The silicon nitride etch mask presents several disadvantages, e.g., it forms pinholes, blisters during the etch process, has a high deposition temperature, and presents a high cost.

Presented here is a novel process using a photosensitive (negative acting), spin-applied, organic polymer etch protective coating that could potentially replace silicon nitride and other metals as an etch mask for wet-etch processes using potassium hydroxide (KOH) or tetramethyl ammonium hydroxide (TMAH) [5]. The coating is spin coated onto the wafer, and a standard photolithography technique is used to create the mask pattern/image on the backside of the wafer. The IC surface side of the wafer could also be protected with a blanket of etch protective coating. In this paper, we have compared the etch protection characteristics of the photosensitive material to LPCVD silicon nitride. Wet-etch tests were done at varying etch times for the formation of vias. A comparison of undercut between the silicon nitride protection and the photosensitive coating protection was conducted to show that ratio of undercut to depth for the photosensitive etch protective coating is constant for stable etching conditions. Effects of other factors such as etch bath concentration and temperature and etch time are also examined.

Key words – through-silicon vias (TSVs), etch protection, 3 D integration, wafer-level packaging



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