IWLPC (Wafer-Level Packaging) Conference Proceedings


Authors: Klaus Ruhmer and Eric Laine et al.
Company: SUSS MicroTec, Inc.
Date Published: 9/17/2007   Conference: IWLPC (Wafer-Level Packaging)

Abstract: Flip Chip as a method for first level interconnects (FLI) has become a mainstream technology in today’s advanced microelectronic packaging applications. This migration from wire bond to flip chip has been fueled by ever increasing demands on electrical performance and package size.

Flip Chip requires the fabrication of solder bumps directly on the wafer. These bumps are commonly manufactured using solder electroplating, especially for fine pitch applications. Wafer level chip scale packaging (WLCSP) typically utilizes solder sphere placement technology to manufacture the bumps. In WLCSP, pitch and solder ball size are usually much higher and the number of I/O much lower than for Flip Chip in Package (FCiP) applications. C4NP (Controlled Collapse Chip Connection New Process) is another suitable technique for a broad range of solder bump pitches, encompassing FCiP to CSP bump dimensions. As the industry migrates to 300mm wafer processing and lead-free flip chip interconnect, C4NP offers unique technological advantages over traditional bumping methods. Due to its nature as a bump transfer technology, it provides high bumping yield and pre-bump inspection and repair capability. Yield is a critical concern for high I/O count applications like microprocessors.

The under bump metallurgy (UBM) structure is a critical component of any solder interconnect system. The UBM typically provides three functions: adhesion to underlying dielectric and metal, barrier to protect the silicon circuitry, and a solder wettable surface. For lead-free bumps, the barrier layer is key to the reliability of the solder joint due to the higher Sn content in the lead free solder. A common barrier layer used in the industry is electroplated nickel. This layer provides good protection from degradation of the silicon metallurgy by tin rich lead free solders. C4NP provides an opportunity to eliminate electroplating, and its associated costs for plating chemistry, analysis, supply and waste treatment.

This paper analyzes electroless Ni/immersion Au (ENIG), with and without Pd as an alternative UBM structure. Wafers were fabricated with these UBM structures, solder applied with C4NP, and chip level stressing performed to determine the robustness of these alternative stack-ups. Analysis of these structures following multiple reflows and thermal cycling is presented.

In addition, the work also discusses production cost analysis based on a cost model specifically developed to determine manufacturability of various UBM structures.

C4NP is a novel solder bumping technology developed by IBM which addresses the limitations of existing bumping technologies by enabling low-cost, fine pitch bumping using a variety of lead-free solder alloys. It is a solder transfer technology where molten solder is injected into pre-fabricated and reusable glass molds. The glass mold contains etched cavities which mirror the bump pattern on the wafer. The filled mold is inspected prior to solder transfer to the wafer to ensure high final yields. Filled mold and wafer are brought into close proximity/soft contact at reflow temperature and solder bumps are transferred onto the entire 300mm (or smaller) wafer in a single process step without the complexities associated with liquid flux.

The data in this paper is provided by the analytical laboratory at Fraunhofer Institute, IZM, Berlin, Germany. UBM formation was done at Fraunhofer IZM. Wafers were bumped using the C4NP process at the IBM Hudson Valley Research Park, Hopewell Junction, NY (USA).

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