IWLPC (Wafer-Level Packaging) Conference Proceedings


LAMINATION TECHNOLOGIES FOR SiP REALIZATION

Authors: Lars Boettcher and Andreas Ostmann et al.
Company: Fraunhofer Institute for Reliability and Microintegration (IZM)
Date Published: 9/17/2007   Conference: IWLPC (Wafer-Level Packaging)


Seika Machinery, Inc.

Abstract: The functional density of electronic systems is unfailingly increasing and is expected to continue so at least within the predictable future. In electronic packaging technology strategies for densification are, however, not as streamlined as in semiconductor industries.

High density packaging realized by 3D stacking is becoming more and more important for consumer electronics that combine more functions and higher memory capacity with significant size shrinkage. Three dimensional chip stacking is the potentially best technology for a semiconductor system integration. Such a technology provides an interesting approach due to its shrinkage capability and signal transmission performance.

Embedding of semiconductor chips into substrates using a lamination technology has several advantages. At first it allows a very high degree of miniaturization, since multiple layers of embedded components can be sequentially stacked. A further advantage is the beneficial electrical performance by short and geometrically well controlled interconnects. Furthermore the embedding gives a homogeneous mechanical environment of the chips, resulting in good reliability.

This paper will present different approaches for cost efficient packaging and SiP realization. All these approaches are based on vacuum lamination of dielectric films and laser via and structuring processes. These process technologies, which are basically used for multi layer printed wiring board production, were adapted to the use on silicon wafer and silicon chips. In both cases further layers can be applied or other components can be conventionally assembled on top. The effect of different lamination parameters on the chip will be discussed. The investigation has shown, that inappropriate lamination can result in chip cracking.

The realization of a thin package for a power MOSFET will be described. Here the chip is embedded into a dielectric layer in between two Cu layers. This construction gives a simple and cost effective package. Thickness of the vertical power IC is 150 µm. Special issues of embedding these relatively thick chips will be discussed. Finally reliability investigations of embedded chips in rigid substrates will be presented, like thermal storage, humidity storage, thermal cycling and moisture level sensitivity. Tests have shown an excellent reliability.

As an example for a wafer level approach using through silicon via (TSV) the development of a chip size SiP will be discussed briefly.

Keywords: 3D packaging, embedded chips, Chip in Polymer, Through Silicon Via, System-in-Package( SiP)



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