Pan Pacific Symposium Conference Proceedings


Authors: Charles Lin, Nick Wang, Len Chen, Ken Chang, Andy Lim, and Jerry Tan
Company: Bridge Semiconductor Corporation
Date Published: 1/31/2007   Conference: Pan Pacific Symposium

Abstract: “Frame Level Packaging” an integrated approach to IC packaging is presented. This packaging technology aims to achieve enhanced package performance by combining the technical advantages of laminate, lead-frame and wafer level packages. Whilst wafer level packaging uses wafer as the processing panel, frame level packaging uses copper frame as the processing panel to build the IC packages with the existing backend infrastructure. Design flexibility and enhanced performance are achievable using the redistribution layer, array terminals and locked copper/solder post features residing on the fortified copper frame. The integrated approach is introduced along with a discussion of how frame level packaging is capable of accommodating different devices, in combination with various interconnect technologies (e.g., wire bonding, flip chip, and surface mounting) within the same package to effect new functionalities. A test vehicle was developed to investigate the reliability of the die paddle designs on the assembled packages using frame level packaging technology platform. Key words: Wafer level package, laminate-based package, lead-frame based package

Members download articles for free:

Not a member yet?

What else do you get when you join SMTA? Read about all of the benefits that go along with membership.

Notice: Sharing of articles is restricted to just your immediate work group. Downloaded papers should not be stored on an external network or shared on the internet.


SMTA Headquarters
6600 City West Parkway, Suite 300
Eden Prairie, MN 55344 USA

Phone +1 952.920.7682
Fax +1 952.926.1819