Pan Pacific Symposium Conference Proceedings


Authors: Dennis Lang and Chung-lin Wu, Ph.D.
Company: Fairchild Semiconductor
Date Published: 1/31/2007   Conference: Pan Pacific Symposium

Abstract: Molded Leaded Packaging is being increasingly adopted in varied applications ranging from cell phone and PDAs to servers and laptop computers. Traditional leaded packages have used the gull wing lead shape to dissipate various physical stresses endured by the package in the application. When package technologies become leadless, such as Quad Flat No-Lead or Micro Lead Frame, it is more sensitive to mechanical loading since there is no or a minimal solder fillet at the side wall of the leads. It becomes necessary for more engineering to be done to verify that the part will not have solder joint failure in the application. This paper will explore various copper trace layouts; solder mask openings, and thickness of PCB design. The stencil design will be varied to examine solder printing. Visual, x-ray and bend testing will be used to evaluate the performance of various solder processes. Varying package form factors ranging from single die, to larger multi-chip modules will be tested. Key words: QFN, MLP, Stencil, Solder Joints

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