Pan Pacific Symposium Conference Proceedings


BGA SOLDER VOID CORRELATION TO VIA-IN-PAD, VIA FILL, SURFACE FINISH, AND LEAD-FREE SOLDER – FINAL REPORT

Authors: Chrys Shea, Rahul Raut, Lou Picchione, Quyen Chu, Nicholas Tokotch, and Paul Wang
Company: ALPHA – A Cookson Electronics Company, Jabil Circuit, and Microsoft Corporation
Date Published: 1/31/2007   Conference: Pan Pacific Symposium


Abstract: The debate on the effect of voiding on BGA reliability has continued for years. Many PWB assemblers strive to minimize voiding, particularly with the advent of lead-free processing and in fine feature area array devices. Although solder pastes have been designed to minimize voiding, and processing guidelines exist to mitigate void formation during reflow processing, the presence of a microvia in a PWB pad can contribute significantly to void formation. It is believed that the depression in the pad caused by the microvia traps air during the stencil printing process, and the air cannot fully escape during reflow. A process of filling the vias with copper at the board fabrication phase, thereby eliminating the depression that contributes to voids, was tested for its effectiveness in void mitigation during assembly. The test compares the voiding results of filled vias with those of unfilled vias and flat pads with no vias at all. The test vehicle and methods, as well as the results of the tests are presented and discussed in detail. KEYWORDS: BGA, Voiding, Lead-Free, Via-In-Pad, Via Fill



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