Pan Pacific Symposium Conference Proceedings


65nm FCBGA RELIABILITY FOR NEXT GENERATION GAMING DEVICE PHASE I-A METHODOLOGY FOR STREAMLINE PRODUCT DESIGN CYCLE AND 2ND AND SYSTEM LEVEL QUALIFICATION

Authors: Paul P.E. Wang, Ph.D., DongJi Xie, Ph.D., Michael Miller, Jelena Larsen, Julia Purtell, Daniel Lau, Daniel Chang, Jerry Tzou, Brian Hung, Hector Marin, Dan Rooney, Ph.D., Chrys Shea, Ravi Bhatkal, Ph.D., and Dongkai Shangguan, Ph.D.
Company: XBOX, Microsoft Corporation, Taiwan Semiconductor Manufacturing Corp, Taiwan Alpha Metals, A Cookson Electronics Inc., Flextronics International
Date Published: 1/31/2007   Conference: Pan Pacific Symposium


Abstract: Increasing demand for graphically virtual reality and computation speed on gaming devices are pushing the process units from current 90nm into 65nm transistor. To make a stride in reducing the problem of power leakage and improving the core performance in clock cycle, new chip design strategy and process technology are required. In this study, a product specific technical consortium is initiated by voluntary participants, including OEM, Chip Supplier, Soldering Material and Fab Supplier, EMS, and Metallurgical/Failure Analytical Lab to study the FCBGA thermal and mechanical reliability. A 65nm FCBGA with electrical daisy chain and thermal die is included in a Test Vehicle (TV) and Box Emulator (BE). To facilitate and streamline the design development cycle, a closed loop Design for Reliability model is proposed. Finite Element Analysis was performed on a test board with almost same probing pin out to see the strain response on the PCB by correlating to gage measurement. Then strain level of the solder joint was benchmarked to the yield strength. The reliability of FCBGA-solder-PCB pad interconnect system will be real-time monitored during Accelerated Thermal Cycling (ATC) in order to assess the interconnect fatigue life and failure mode. In order to derive the mechanical residual stress correlation to the reliability scale, a four-point bending test fixture will be used to apply levels of stress before ATC is conducted on the stressed interconnect system. Finite Element Modeling will be performed to study the strain level in the solder interconnect to provide insights for fatigue life estimation. Extensive metallurgical analyses will be conducted at time zero as well as during the ATC to reveal solder crack growth, intermetallic compound evolution and interfacial grain structure. The thermal interconnect management system, Process Unit-Thermal Interface Material-Heatsink-Fan, contained in the Box Emulator, is used to derive the die junction temperature (Tj) and thermal resistance (Rth) at various interconnect interfaces. Thermal degradation of the system, particularly the Thermal Interface Material (TIM), is also assessed by thermally stressing the system in ATC then plotting the Tj and Rth variation in time series. Key words: closed loop Design for Reliability,



Members download articles for free:

Not a member yet?

What else do you get when you join SMTA? Read about all of the benefits that go along with membership.

Notice: Sharing of articles is restricted to just your immediate work group. Downloaded papers should not be stored on an external network or shared on the internet.


Back


SMTA Headquarters
6600 City West Parkway, Suite 300
Eden Prairie, MN 55344 USA

Phone 952.920.7682
Fax 952.926.1819