Surface Mount International Conference Proceedings


Author: Jason D. Brown
Company: Compaq Computer Corporation
Date Published: 9/10/1996   Conference: Surface Mount International

Abstract: Array packages have established themselves as the package of choice over PQPP for high pin count applications. The steps in establishing this position have been met with many challenges. One of the major challenges has been PCB routability. The first step in the improvement of PCB routability was the shift from full array packages to peripheral arrays. This change included a reduction in pitch from 1.5mrn to 1.27rnm. The finer pitch allowed for higher pin counts in the same body sizes. As the industry requirement for I/O increases, the four row package designs could not keep up with the need for more pins. The introduction of the 5-row peripheral designs allowed for an approximately 20% increase in the number of the available interconnects. This jump to the 5-row peripheral array package raised concerns about PCB routability. Changes in the typical PCB design rules were needed. The options were to increase the PCB layer count and use the standard 0.024” pad diameter with .006” lines and spaces or reduce the PCB geometry and route the design in 4 layers2. The second option brought about concerns for solder joint reliability due to the reduction of the solder pad diameter. The figure below shows the PCB routing, using 20-mil pad, required for a 5-row, 1.27mrnpitch perimeter BGA. This paper examines the effect pad diameter reduction has on manufacturability, rework and reliability.

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