Pan Pacific Symposium Conference Proceedings


A STUDY ON COPPER ELECTRODEPOSITION USED FOR VIA INTERCONNECTION, FOR THE APPLICATION OF WAFER LEVEL PACKAGING

Authors: SeungJin Oh, YoonChul Sohn, WoonBae Kim, KeDong Baek, and ChangYoul Moon
Company: Samsung Advanced Institute of Technology
Date Published: 1/31/2007   Conference: Pan Pacific Symposium


Abstract: Copper electrodeposition to fill vias of electrical interconnection, which will be used for wafer level packaging of IC and RF devices, was performed. Via hole was either through-hole type or blind via. When it comes to through-hole type via, it is also applicable for an interposer (organic or silicon one). Both types of vias were filled with plated copper; in copper sulfate based solution containing chloride, suppressor, accelerator, leveler, pulse plating was adopted with reverse current application. By getting optimum condition for plating such as current shape and additive composition, we could get void-free via filling, which possibly leads to enhanced reliability of devices. Furthermore, growth shape was observed by varying the applied current density such as 20 and 40 mA/cm2, in order to disclose the role of suppressor and leveler in nucleation and growth stages of electrodeposition. The 2-dimensional and 3-dimensional (3D) metal phase formation either phase transition (nucleation) or cluster growth were discussed in relation with suppressing role of additives in electrodepositon, from the SEM observation. On the basis of the electrochemical and metallurgical consideration of copper electrodeposition used in via filling, we are going to accomplish perfect filling of via with higher aspect ratio. Key words: electrodeposition, via, plating, WLP, microstructure, SEM.



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