IWLPC (Wafer-Level Packaging) Conference Proceedings


SINGLE WAFER BUMPING

Authors: Yixiang Xie, Qiang Fu, and Solomon Basame
Company: Surfect Technologies, Inc.
Date Published: 11/1/2006   Conference: IWLPC (Wafer-Level Packaging)


Abstract: The rapid growth in demand for bumped wafers is forecast to grow exponentially over the next ten years at a growth rate of 28.1% a year according to a research firm1. The key to win this growing market is to lower the cost of bumping wafers through the use of lower cost plating equipment and methods. The combination of lower cost equipment with novel process development will enable new applications and emerging markets. Low cost single wafer plating units have been designed and tested for 200 and 300 mm wafers, board plating manufacturing, and R&D facilities. The units not only apply to electrolytic plating but also are used in electroless plating processes. Single metal, multi-metal plating, and nano-particle plating processes have been developed in the units with smallest line feature of 20 µm and open via diameter of 50 µm. In this paper, single layer, multi-layer metals, metal alloy, and metal capsulation plating process, resulted images, and uniformity will be discussed.

Key words: Bumping, Plating, Interconnect, innovation



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